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Please click here. CMP Total Solution Service Business For further details, please click here. New 200 mm Patterned Wafers for 3DNAND Flash Memory Process Development For further details, please click here. New 200mm and 300mm TSV CMP Test Patterned Wafer, January 2013 New 200mm and 300mm TSV CMP test patterned wafers are based upon the test patterned mask designed by IZM-ASSID Fraunhofer. There are three different types of TSV CMP test patterned wafers. They are: 1) Cu CMP TSV process characterization wafer; 2) bonded wafer for backside device Si wafer grinding process development; and 3) backside device wafer Si thinning process characterization wafers. In order to manufacture these three types of new TSV CMP test patterned wafers, the following process technology and equipment are used: 1. Cu plating: Fountain Plating System Among all the TSV CMP test patterned wafers, 300mm wafers are available immediately. 200mm test patterned wafers will be available by around the middle part of this March. For further details, please click here. Micro-Chevron Test Patterned Wafer For Wafer Bond Strength Characterization, March 2011 3D integration techniques require the characterization of wafer bonding processes as an essential part of the optimal implementation into stacked IC architectures. In the case of conventional characterization techniques, such as 3-pt and 4-pt bending, samples are prepared after bonding and require a special pre-crack which is used to help determine the bond quality. The accuracy and repeatability of these measurements is influenced by the pre-crack depth which is difficult to control especially for intermediate bonding where film thickness uniformity can vary over the surface of the stack. The micro-chevron test is an evolution in wafer bond characterization. Although the chevron notch has been used for many years to test the fracture toughness of brittle materials, only recently has work been done to use it to evaluate the quality of bonded wafers. The integration of a chevron notch, at the bond interface eliminates the challenges of creating a pre-crack during sample preparation. The notch structure is patterned on to one of the wafers in the stack using photolithography and etching processes. These notched samples are evaluated using conventional testing tools with minor modifications to the test fixtures. Under an agreement with the College of Nanoscale Science and Engineering, SUNY-Albany, we are happy to announce the establishment of new micro-chevron test patterned wafers. Using these test patterned wafers our customers will be able to test a variety of bonds including Cu-Cu and BCB-Si. For various 200mm test patterned wafer product offerings, metrology plan and characterization services, please contact us. 200mm and 300mm Standardized Test Patterned Wafers For Bonding Process Applications, September 2010 In 3D IC manufacturing and applications of TSV technology, wafer bonding is one of the most critical process steps. With the advancement in wafer bonding process, there is urgent need to quickly measure and quantify interfaces created by 3D processing for process and equipment qualification. With mutual agreement with SUSS Microtec, we are happy to announce establishment of new standardized test patterned wafers for 3D-IC wafer bonding applications. Using these standardized test patterned wafers, our customers will be able to check post-bond alignment bond quality, bond strength, hermaticity and electrical performance. There are two types of test patterned wafers: 1) the wafers based upon SUSS Microtec's mask design; and 2) new wafers based upon SKW CMP test patterned wafer mask design for defect characterization. Our initial product offerings are: 1) 4 200mm test patterned wafers; and 2) 4 300mm test patterned wafers. For further details, please click here. 200mm TSV Cu CMP Test Patterned Wafers With 20µm and 50µm Si Trench Depth (SKW6-TSV4-20µ and SKW6-TSV4-50µ), March 2010 For further details, please contact SKW Associates at (408) 919-0094 or skw@testwafer.com. 200mm TSV Test Patterned Wafer For Backside Si Layer Thinning Process Optimization (SKW6-TSV4G-20µ), March 2010 For further details, please contact SKW Associates at (408) 919-0094 or skw@testwafer.com. 300mm TSV Cu CMP Patterned Wafers (SKW6-TSV3-2 and SKW6-TSV3-NT), October 2009 For further details, please click here. Updated Wafer Product List For Both 200mm and 300mm Blanket and Patterned Wafers, July 2009 For updated wafer product list (for both 200mm and 300mm blanket and patterned wafers), please click here. 200mm TSV Cu CMP Test Patterned wafer ( SKW6-TSV3), July 2009 Through silicon vias (TSV's) are a key component in 3-D interconnect. TSV's improve electrical performance, reduce power consumption and shrink device sizes. Manufacturing TSV's involves via etching, filling and CMP. New test patterned wafer (SKW6-TSV3) has been introduced. In this new test patterned wafer, two major features are: contact arrays (ranges from 10µm - 200µm) and line/spacing arrays (ranges from 5µm - 150µm). For further details, please click here. 200mm GST CMP Test Patterned Wafer (SKW8), July 2009 Phase-change memory (PCM) is a type of non-volatile computer memory. PCM uses the unique behavior of chalcogenide glass, which can be "switched" between two states, crystalline and amorphous, with the application of heat. In order to fabricate the PCM device with high integration, CMP of thin chalcogenide (Ge2Sb2Te5) [GST] is required. For optimization of consumable sets, GST blanket and test patterned wafers have been introduced. We have currently one type of GST blanket wafer and two different types of GST CMP test patterned wafers: SKW8O-GST; and SKW8N-GST. Please click here for further information. 300mm Cu Test Patterned wafer ( SKW 6-ATR-40), July 2008 New 300mm Cu test patterned wafers (SKW 6-ATR-40) are introduced. The minimum feature size of this 65nm technology node wafer is 0.09 µm. With advanced e-testing features and intelligent dummy additions, these new types of 300mm test patterned wafers should have various technical advantages over other types of 65 nm technology node CMP process characterization and analysis test patterned wafers. We have currently six different types of ATR-40: ATR-40 Cu/ TEOS; ATR-40 Cu/Coral; ATR-40 Cu/Coral/TEOS cap; ATR-40 Cu/BDI; ATR-40 Cu/BDI/TEOS cap; and ATR-40 Cu/BDIx/TEOS cap wafers. Please click on each individual item for further information related to each new type of Cu CMP patterned wafer. 300mm W plug patterned wafer ( SKW 5-ATR-35P), July 2008 New 300mm W plug patterned wafers ( SKW 5-ATR-35P) are introduced. The minimum plug size ranges from 0.11 µm to 0.2 µm. The pattern density is up to 20% (from ~5%). Because of the size of the plug holes and pattern density variation, proper characterization of post-W CMP process requires focused-ion-beam(FIB) SEM. Please click here for the wafer specifications related to this advanced 300mm W plug pattern wafer. New STI CMP Patterned 200mm and 300mm wafers (SKW 3-9), January 2008 New STI CMP patterned 200mm and 300mm wafers are introduced. Our current SKW 3-2 wafers (based upon MIT test patterned design) have been shown to be fairly ineffective in the use for advanced STI CMP process characterization. Particularly, it is quite difficult to carry out end-point-detection(EPD) routine for SKW 3-2 wafers because of: 1.) too wide pattern
density range (0-100%) In the case of our new STI CMP test patterned mask(SKW 3-9) wafers, the following modifications from SKW 3-2 have been made: 1.) die size: 14mm
x 16mm (instead of 20mm x 20mm) Currently, we have
one SKW 3-9 200mm product (HDP CVD oxide version) and two 300mm SKW 3-9
products( HDP and HARP CVD oxide versions). Please click New W Plug patterned 200mm wafer, SKW 5-RSAX, June 2008 New W plug patterned 200mm wafer, SKW 5-RSAX has been introduced. This current W plug patterned wafer, SKW 5-J085, was introduced about 2 years ago and has been well received among CMP infrastructure companies. However, this patterned wafer has a couple of weaknesses. The first weakness is its plug size variation (only 0.15µm-0.2µm). The second one is its very narrow plug array patterned density variation (~5%-7%). Our new W plug patterned 200mm wafer, SKW 5-RSAX, can make up for these two deficiencies. The plug sizes are 0.2µm and 0.7µm and the pattern density variation is 4%-25%. These two factors from SKW 5-RSAX make our new W plug patterned wafer a very valuable addition and compliment our current SKW 5-J085 wafer product. Please click here for the wafer specification related to this new 200mm W plug patterned wafer. New
200mm Cu test patterned wafer (SKW6-6). New
300mm Cu Test Patterned Wafer (SKW ATR-35). New
W Plug Patterned Wafer SKW5-J085
for 90nm Technology Node, November 2005.
New
CMP Test Patterned 300mm Wafers Introduced, January 2005
Second
XE-300 Atomic Force Microscope/Atomic Force Profiler (Integrated with
ChampiAn Software), December 2004
New W
CMP Plug Patterned Wafer, November 2004 SKW Associates'
ChampiAn Software Has Been Integrated into PSIA
XE-300P Long Range Scan Atomic Force Profiler, September 2004 Daisy
Chain Test Patterned Wafers For Packaging Process Development, September
2004 2"
CMP Test Patterned Wafers, July 2004
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SKW
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